A computer including a controlling node (a control node) and an arithmetic node (a calculation node) is known.
For example, Patent Document 1 discloses an information processing apparatus that has a control core (a control node) with an operating system incorporated and at least one calculation core (a calculation node) controlled by the control core and configured to execute predetermined calculation processing. According to Patent Document 1, the control core has a calculation core control part that instructs a stopped calculation core to start calculation processing to be executed by the calculation core. Moreover, the calculation core includes a calculation processing control part that starts calculation processing in response to an instruction from the calculation core control part, and an exception detection part that detects exception processing having occurred during execution of calculation processing and stops execution of calculation processing in which exception processing has occurred. According to Patent Document 1, the abovementioned configuration makes it possible to suppress interference by the OS (Operating System) and so on.
Patent Document 1: Japanese Unexamined Patent Application Publication No. JP-A 2015-094974
In the case of the technique as disclosed by Patent Document 1, access to a memory included by the calculation node is performed, for example, in a manner that an arithmetic device such as a processor accesses a PCI (Peripheral Component Interconnect) memory space with the use of a mechanism of memory-mapped I/O. Herein, the size of the PCI memory space is set by BIOS (Basic Input Output System) or OS of the control node serving as a host. Therefore, even if the calculation node is equipped with a memory which is equal to or more than the PCI memory space supported by the control node, the size of a memory which can be used by the control node is limited to the size of the PCI memory space. Consequently, there has been a problem that it is difficult to efficiently utilize the memory mounted on the calculation node.
Further, the PCI memory space is a physical address. Therefore, for example, when a context switch to change calculation processing being executed in the calculation node is performed, if data loaded in the memory of the calculation node is simply saved, there is no data to be referred to at a physical address used by RDMA (remote Direct Memory Access) such as InfiniBand. Moreover, regarding sites which are not used by the RDMA, allocation of physical addresses is managed by an MMU (Memory Management Unit) of the host, so that it is required to reset the MMU in order to save the data. Because of the reasons as described above, with the technique disclosed by Patent Document 1, it is difficult to save data loaded in the memory of the calculation node when a context switch is performed. Consequently, there has been a problem that it is difficult to efficiently utilize the memory mounted on the calculation node.
Thus, there has been a problem that it is difficult to efficiently utilize the memory mounted on the calculation node.